Design Engineering Manager, Project Manager
2001-3 Managed engineering design team to develop 10 Giga bit Ethernet PHYs, and PCI-Express chips. I managed schedules, design reviews; also did hands on work with Synthesis & timing (.13micron),
did initial place and route, assist with lab validation & debug; Worked closely with analog team, and with backend P&R and Layout engineers. Had overall responsibility for the
10 Gig mixed signal data comm chips.
2004-8 Project Manager over 30 chips, to 55nm; work with marketing, customers,
Fab & assembly house, ATE test, validation groups, qualification,
and help develop internal procedures; have overall responsibility for 10 Gig products, Video product line, IP, ISO 9001.
ASIC Design Engineer, Project lead
Project lead for 7 disk drive controller ASICs; working closely with silicon vendors, inside teams and
outside consultants; set schedules, propose architecture requirements and specifications.
Worked on 3 additional digital ASICs, from start to mass-production,
as a hands-on design & test engineer.
My main contributions were in motor servo tracking,
and buffer arbitration with host interface and embedded processor.
Used Verilog HDL for logic, simulation and test vectors.
Synopsys to synthesize for NEC, Lucent, and TI, standard cell and gate arrays,
0.5 through 0.13 micron libraries.
Helped debug circuit boards and firmware to bring-up ASICs.
Led investigations in thermo analysis and low power design.
